Nearing end of bus-based architecture today
One more generation of today’s bus-based architecture
- multi-level signaling
- 1000+ chip IO
- exotic packaging and PCB technology
- IB and LVDS at 2.5 Gb/s
New approach needed for products in 2004
- signal integrity focus for electronics
- switched-based architecture
- seamless integration of optical technology
USC PONI-ROPE PCB area < 50% ICs, surface mount packages,
12-metal layers, Gb/s per signal line,
de-skewed signal lines to +/- 10 ps,
5 mil lines, 7 mil spaces