PPT Slide

IO interconnection and packaging in a large system

Large system IO as function of gates per chip follows Rents rule (IO/k)1.8 = number of gates

Multi-shelf in a frame

Gates per chip in millions

0.01

0.1

1.0

10

100

0.01

0.1

1.0

10

100

1000

Packaging option

k represents sharing

in interconnects

Multi-PCB in a shelf

Multi-HPMCM on PCB

High performance multi-chip module

surface mount on PCB

1460 IO from PCB

900 IO from MCM

3260 IO from MCM

5300 IO from PCB

3D HPMCM

k=0.1 for frame (six shelves max)

k=0.2 for shelf (ten PCBs max)

k=0.3 for PCB (four HPMCM max)

k=0.4 for HPMCM (ten ICs max)

k=0.5 for IC

Frame

IC

T

otal IC

I/O terminals required (thousands)

J. Lightwave Technol. 10, 811 (1992)

~ billion

transistors

Conventional economies of scale and system diversity drive multi-chip solution

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