StrongARM low-power microprocessor design

• 2.5M transistors, 160 MHz, 2.1 MIPS, 32b, 0.5 W, internal VDD = 1.6 V, 7.8x6.4 = 50 mm2 three-metal 0.35 mm CMOS, 144 pin QFP package

• To minimize pin power and support a high-speed internal core, 50% of chip area is devoted to two 16 kB Dcache and Icache

• 90% of the transistors are devoted to Dcache and Icache

• The pad ring occupies 33% of chip area and the processor core fills the remaining 17% of chip area.

Source: IEEE J. Solid-state circuits 31, 1703 (1996)

Power dissipation

Icache 27%

Ibox 18%

Dcashe 16%

Clock 10%

IMMU 9%

Ebox 8%

DMMU 8%

Write buffer 2%

Bus interface 2%

PLL ə%

Previous slide

Next slide

Back to first slide

View graphic version