Future high-performance microprocessor architecture

64 bit words

? = 10 GHz

Total 8, 32-bit instructions /??

Total 2, 64-bit data / ?

Power = 100 W

Single chip VLIW or MP with integrated

L0 Cache

80% scalar hit rate

1 ns

64 kByte

L0 Cache

480 GByte/s

CPU-0

CPU-1

CPU-2

CPU-3

L1 Cache

80% scalar hit rate

100 GByte/s

3-10 ns

8 MByte

L1 Cache

20 GByte/s

Main Memory

3-30 ns

10 GByte local

3-1000 ns

1 TByte network

Scalar: 800 Gb/s communication channel

< 4 W total micro-photonic power

162 W electrical rambus power consumption

Vector: 4.8 Tb/s communication channel

< 19 W total micro-photonic power

7.8 kW electrical rambus power consumption

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